The present invention relates generally to nonvolatile memory technology. More particularly, the present invention relates to a non-boosting program-inhibit scheme used in NAND flash memory design with low-voltage page buffer. Applications of the present invention can be expanded to current NAND design to HiNAND string and array by using a direct, non-boosting scheme to achieve more reliable program-inhibit operation, though more applications may be recognized on all Nonvolatile memory (NVM) cells that are using the similar extremely low current FN-channel erase and FN-channel program.
Nonvolatile memory is well known in the art. The different types of nonvolatile memory that employ a charge retention mechanism include Read-Only-Memory (ROM), Electrically Programmable Read Only Memory (EPROM), Electrically Erasable Programmable Read Only Memory (EEPROM), NOR Flash Memory, and NAND Flash Memory. The charge retention mechanism may be charge storage, as in a floating gate memory cell, a so-called Flash-based cell.
The NAND Flash memory cell design has several advantages. Firstly, its cell size is highly scalable and is able to have a cell size that is a factor of approximately four times (4×) larger than the minimum feature size (λ2) of the manufacturing technology. This has held in technologies with feature sizes from 0.25 μm down to 20 nm. This is the smallest nonvolatile memory cell when compared to other nonvolatile cell types. Secondly, NAND Flash memory cell design uses a low-current Fowler-Nordheim (FN) tunneling phenomena for both program and erase operations. The FN tunneling allows the program and erase operations to be performed in relatively larger memory unit sizes and a faster speed. The FN erase operation is typically performed in a unit of a large sector with sizes ranging from 512 Kb to 2 Mb and 1 ms fast erase time in current specifications. The FN program is performed in a unit of a large page size varying from 512 B to 2 KB with a fast speed of 200 μs typically in the current specifications. Like EEPROM and NOR flash, NAND Flash memory provides the repeatedly in-system or in-circuit electrically programmable and erasable functions with the lowest die cost.
The major NAND cell and the cell array structures and operations from different NAND memory chip manufacturers are very similar. The mainstream NAND cells are either made of 2-poly floating-gate NMOS or 1-poly charge-trapping NMOS storage devices. In a charge trapping mechanism, as in a Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) or Metal-Oxide-Nitride-Oxide-Silicon (MONOS) type cell, the charge is trapped in a charge trapping layer between two insulating layers. The charge trapping layer in the SONOS/MONOS devices has a relatively high dielectric constant (k) such Silicon Nitride (SiNx).
Currently, the mainstream standalone NAND in mass production is mainly based only 2-poly floating-gate NMOS device. The NAND flash is employing the extremely HV (high-voltage) but low current FN channel-erase and FN channel-program scheme to change the stored data. In the traditional NAND designs a local-boosting program-inhibit scheme is adopted to generate 7V in the selected NAND cell's channel to suppress FN program, which is unreliable. Furthermore, an on-chip HV charge-pump must be active all the times during the program and program-inhibit operations. Therefore it is desired to have a fast and low-current program and program-inhibit operations. As oppose to the existing unreliable local-boosting program inhibit scheme to generate 7V in the selected NAND cell's channel to suppress FN program in today's NAND, a direct, non-boosting scheme to achieve more reliable program-inhibit operation is preferred.
Furthermore, it is desirable to have improved NAND array design so that the operations of those popular NAND string and array with their cells employing the similar write scheme of HV but low-current FN channel-erase and FN channel-program can allow the use of very compact LV (low-voltage) page buffer and smaller HV charge-pump circuit for achieving drastic reduction in both die size and power consumption in write operation.
Therefore, improved NAND operation schemes as well as new NAND memory array architectures are needed and become objectives of the present invention.